----------------------------------------------------------------------
-- This file was created by the Xilinx CORE Generator tool, and     --
-- is (c) Xilinx, Inc. 1998, 1999. No part of this file may be      --
-- transmitted to any third party (other than intended by Xilinx)   --
-- or used without a Xilinx programmable or hardwire device without --
-- Xilinx's prior written permission.                               --
----------------------------------------------------------------------

-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component vfft256
	port(
		clk		: in std_logic;
		rs		: in std_logic;
		start		: in std_logic;
		ce		: in std_logic;
		scale_mode	: in std_logic;											-- control
		di_r		: in std_logic_vector(15 downto 0);
		di_i		: in std_logic_vector(15 downto 0);
		fwd_inv	: in std_logic;			
		io_mode0	: in std_logic;	
		io_mode1	: in std_logic;
		mwr		: in std_logic;
		mrd		: in std_logic;
		ovflo		: out std_logic;		
		result	: out std_logic;		
		mode_ce	: out std_logic;
		done		: out std_logic;		
		edone		: out std_logic;	
		io		: out std_logic;
		eio		: out std_logic;
		bank		: out std_logic;
		busy		: out std_logic;		
		wea		: out std_logic;			
		wea_x		: out std_logic;
		wea_y		: out std_logic;
		web_x		: out std_logic;
		web_y		: out std_logic;
		ena_x		: out std_logic;
		ena_y		: out std_logic;
		index		: out std_logic_vector(7 downto 0);	
		addrr_x	: out std_logic_vector(7 downto 0);	
            addrr_y     : out std_logic_vector(7 downto 0);		
		addrw_x	: out std_logic_vector(7 downto 0);		
		addrw_y	: out std_logic_vector(7 downto 0);		
		xk_r		: out std_logic_vector(15 downto 0);	
		xk_i		: out std_logic_vector(15 downto 0);	
		yk_r		: out std_logic_vector(15 downto 0);	
		yk_i		: out std_logic_vector(15 downto 0));
end component;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- Synplicity black box attribute definitions 
  
attribute black_box : boolean; 
attribute black_box of your_component_name : component is true; 
  
-- FPGA Express black box attribute definitions 

attribute fpga_dont_touch : string; 
attribute fpga_dont_touch of your_component_name : component is "true"; 

-- XST black box attribute definitions 

attribute box_type :  string; 
attribute box_type of your_component_name :  component  is "black_box";

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
yourinstance : vfft256
	port map(
		clk		=> clk,
		rs		=> rs,
		start		=> start,
		ce		=> ce,
		scale_mode	=> scale_mode,								
		di_r		=> di_r,
		di_i		=> di_i,
		fwd_inv	=> fwd_inv,
		io_mode0	=> io_mode0,
		io_mode1	=> io_mode1,
		mwr		=> mwr,
		mrd		=> mrd,
		ovflo		=> ovflo,
		result	=> result,
		mode_ce	=> mode_ce,
		done		=> done,
		edone		=> edone,
		io		=> io,
		eio		=> eio,
		bank		=> bank,
		busy		=> busy,
		wea		=> wea,
		wea_x		=> wea_x,
		wea_y		=> wea_y,
		web_x		=> web_x,
		web_y		=> web_y,
		ena_x		=> ena_x,
		ena_y		=> ena_y,
		index		=> index,
		addrr_x	=> addrr_x,
            addrr_y     => addrr_y,
		addrw_x	=> addrw_x,		
		addrw_y	=> addrw_y,	
		xk_r		=> xk_r,
		xk_i		=> xk_i,
		yk_r		=> yk_r,
		yk_i		=> yk_i	
	    );

-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- The following code must appear above the VHDL configuration
-- declaration.  An example is given at the end of this file.

---------------- Begin Cut here for LIBRARY Declaration ---- LIB_TAG

-- synopsys translate_off

Library XilinxCoreLib;
Use XilinxCoreLib.vfft256_comp.all;

-- synopsys translate_on

-- LIB_TAG_END ------ End LIBRARY Declaration --------